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1 www.semtech.com sc4808a/b high performance dual ended pwm controller power management revision october 20, 2005 description features applications typical application circuit ? 120a starting current ? pulse by pulse current limit ? programmable operation up to 1mhz ? internal soft start ? programmable line undervoltage lockout ? over current shutdown ? dual output drive stages on push-pull configuration ? programmable internal slope compensation ? programmable mode of operation (peak current mode or voltage mode) ? external frequency synchronization ? bi-phase mode of operation ? -40 to 105 c operating temperature ? 10 pin msop lead free package available. weee and rohs compliant. ? ? ? ? ? telecom equipment and power supplies ? ? ? ? ? networking power supplies ? industrial power supplies ? push-pull converter ? half bridge converter ? full bridge converter ? isolated vrm?s vo vin rsense gnd_out sync gnd_in fb gnd ref luvlo outa outb cs vcc sync rc sc4808 the sc4808a/b is a dual-ended, high frequency, integrated pwm controller, optimized for isolated applications that require minimum space. it can be configured for current or voltage mode operation with required control circuitry where secondary side error amplifier is used. some of the key features are high frequency operation of 1 mhz that allows the use of smaller components thus saving cost and valuable board space. an internal ramp on the current sense pin allows internal slope compensation programmed by an external resistor. other features include programmable frequency up to 1mhz, pulse by pulse current and line monitoring input with hysteresis to reduce stress on the power components. a unique oscillator is used to synchronize two sc4808?s to work out of phase. this minimizes the input and output ripple thus reducing noise on the output line and reducing stress and size of input/output filter components. the dual outputs can be configured in push-pull, half bridge and full bridge format with programmable dead time between two outputs depending on the size of the timing components. the sc4808 also features a turn on threshold of 12v for sc4808a and 4.4v for sc4808b. they are available in msop-10 packages.
2 ? 2005 semtech corp. www.semtech.com sc4808a/b power management absolute maximum ratings electrical characteristics r e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a mt i n u m w p e l c y c y t u d m u m i x a m, v 5 = b f , z h k 0 5 = c s o f b t u o r o a t u o t a d e r u s a e m 8 49 40 5% e l c y c y t u d m u m i n i m, v 5 . 1 = b f , z h k 0 5 = c s o f b t u o r o a t u o t a d e r u s a e m 0% e s n e s t n e r r u c n i a g 3 l a n g i s t u p n i m u m i x a m 5 7 45 2 55 7 5v m y a l e d t u p t u o o t s c 0 0 1s n d l o h s e r h t t n e r r u c r e v o 0 5 8 .0 5 9 .1v n o i t a s n e p m o c e p o l s l a n r e t n i r o t s i s e r 5 2k ? t e s f f o s c o t b f 0 3 . 10 5 . 10 7 . 1v t u p t u o l e v e l w o l t u o 00 5 .0 7 .v l e v e l h g i h t u o 0 . 1 15 2 . 1 10 0 . 2 1v e m i t e s i r 5 2s n e m i t l l a f 5 2s n r e t e m a r a pl o b m y sm u m i x a ms t i n u e g a t l o v y l p p u sv c c 8 1 o t 5 . 0 -v t n e r r u c y l p p u si c c 0 2a m d n g o t f e r , o l v u l , s c , c r , c n y s 7 o t 5 . 0 -v d n g o t b fv b f v ( o t 5 . 0 - f e r ) 5 . 0 +v t n e r r u c f e ri f e r 0 1a m d n g o t b t u o / a t u ov b / a t u o 8 1 o t 5 . 0 -v ) k a e p ( t n e r r u c e c r u o s b t u o / a t u oi e c r u o s 0 5 2 -a m ) k a e p ( t n e r r u c k n i s b t u o / a t u oi k n i s 0 5 2a m t t a n o i t a p i s s i d r e w o p a c 5 2 =p d 5 0 1 . 1w e c n a t s i s e r l a m r e h t a j 1 . 3 1 1w / c e r u t a r e p m e t n o i t c n u jt j 0 5 1 o t 0 4 -c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 o t 5 6 -c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3 +c ) l e d o m y d o b n a m u h ( g n i t a r d s ev d s e 2v k unless specified: vcc = 12v; cl = 100pf; t a = -40c to 105c exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied.
3 ? 2005 semtech corp. www.semtech.com sc4808a/b power management electrical characteristics (cont.) r e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a mt i n u t u o k c o l e g a t l o v r e d n u c c v ) a 8 0 8 4 c s ( d l o h s e r h t t r a t s 5 7 . 0 12 15 2 . 3 1v ) a 8 0 8 4 c s ( s i s e r e t s y h 5 . 35 . 45 . 5v ) b 8 0 8 4 c s ( d l o h s e r h t t r a t s 0 . 40 4 . 45 . 4v ) b 8 0 8 4 c s ( s i s e r e t s y h 0 40 70 1 1v m t u o k c o l e g a t l o v r e d n u e n i l d l o h s e r h t t r a t sk 4 1 = 3 2 r ? k 0 1 = 3 3 r , ? ) 4 1 e g a p e e s (% 3 -f e r v% 3 +v s i s e r e t s y hk 4 1 = 3 2 r ? k 0 1 = 3 3 r , ? ) 4 1 e g a p e e s ( f o % 6 . 5 f e r v v m t r a t s t f o s p m a r t r a t s t f o s l a n r e t n i 0 0 2v / s ) a 8 0 8 4 c s ( n o i t a r u d t r a t s t f o sk 7 = s c r ? n o i t a c i l p p a e h t n i a l u m r o f e e s ( ) 1 2 e g a p n o n o i t c e s n o i t a m r o f n i 0 1 1s ) b 8 0 8 4 c s ( n o i t a r u d t r a t s t f o sk 1 = s c r ? n o i t a c i l p p a e h t n i a l u m r o f e e s ( ) 1 2 e g a p n o n o i t c e s n o i t a m r o f n i 2 1s y a l e d t r a t s t f o s 0 4 1s r o t a l l i c s o y c n e u q e r f r o t a l l i c s or c s o k 1 1 = ? c , c s o f p 0 0 2 =0 5 40 0 50 5 5z h k p m a r r o t a l l i c s o 2 / f e r v 5 2 . 0 + v e c n a t i c a p a c d n g o t n i p c r 2 2f p e g n a r y c n e u q e r f r o t a l l i c s o 0 50 0 0 1z h k k c o l c / c n y s ) a 8 0 8 4 c s ( d l o h s e r h t c n y s k c o l c 6 . 1v ) b 8 0 8 4 c s ( d l o h s e r h t c n y s k c o l c 0 . 1v e g n a r y c n e u q e r f c n y s f c s o 3 . 1 *z h k p a g d n a b ) a 8 0 8 4 c s ( e g a t l o v e c n e r e f e r 5 7 . 40 . 55 2 . 5v ) a 8 0 8 4 c s ( t n e r r u c e c n e r e f e r 5a m ) b 8 0 8 4 c s ( e g a t l o v e c n e r e f e r 0 7 9 . 25 2 1 . 30 8 2 . 3v e c n e r e f e r) b 8 0 8 4 c s ( t n e r r u c 5a m l l a r e v o t n e r r u c p u t r a t sd l o h s e r h t t r a t s < c c v0 5 1a t n e r r u c y l p p u s g n i t a r e p ov 0 = s c , v 0 = b f7a m e g a t l o v t n u h s r e n e z c c va m 0 1 = d d i6 1v unless specified: vcc = 12v; cl = 100pf; t a = -40c to 105c
4 ? 2005 semtech corp. www.semtech.com sc4808a/b power management pin configuration ordering information r e b m u n t r a pe g a k c a pt ( e g n a r . p m e t a ) r t s m i a 8 0 8 4 c s ) 1 ( 0 1 - p o s mc 5 0 1 o t c 0 4 - t r t s m i a 8 0 8 4 c s ) 2 ( ) 1 ( r t s m i b 8 0 8 4 c s ) 1 ( t r t s m i b 8 0 8 4 c s ) 2 ( ) 1 ( (msop-10) top view notes: (1) only available in tape and reel packaging. a reel contains 2500 devices. (2) lead free product. this product is fully weee and rohs compliant.
5 ? 2005 semtech corp. www.semtech.com sc4808a/b power management fb: the inverting input to the pwm comparator. stray in- ductances and parasitic capacitance should be minimized by utilizing ground planes and correct layout guide lines (see page 22). ref: bandgap reference output it should be by passed with a 2.2uf low esr capacitance, right at the ic pin. cs: current sense input and internal slope compensation are both provided via the cs pin. the current sense input from a sense resistor is used for the peak current and overcurrent comparators. an internal 1 to 3 feed back volt- age divider provides a 3x amplification of the cs signal. this is used for comparison to the external error amplifier signal. if an external resistor is connected from cs to the current sense resistor, the internal current source will pro- vide a programmable slope compensation. the value of the resistor will determine the level of compensation. at higher compensation levels, voltage mode of operation can be achieved. rc: the oscillator programming pin. the oscillator should be referenced to a stable reference voltage for an accu- rate and stable frequency. only two components are re- quired to program the oscillator, a resistor (tied to vref and rc), and a capacitor (tied to the rc and gnd). the follow- ing formula can be used for a close approximation of the oscillator frequency. 8 . 0 1 _ ? tot osc a osc c r f 9 . 0 1 _ ? tot osc b osc c r f where: circuit sc osc tot c c c c + + = 4808 pf c sc 22 4808 ? where the frequency is in hertz, resistance in ohms, and capacitance in farads. the recommended range of timing resistors is between 10 kohm and 200kohm and range of timing capacitors is between 100pf and 1000pf. timing resistors less than 10 kohm should be avoided. refer to layout guide lines on page 22 to achieve best re- sults. luvlo: line undervoltage lockout pin. an external resis- tive divider will program the undervoltage lockout level. the external divider should be referenced to the quiet analog ground (see page 22). during the luvlo, the driver out- puts are disabled and the softstart is reset. this pin can also function as an enable/disable. sync: sync is a positive edge triggered input with a thresh- old set to 1.6v (sc4808a), and 1.0v (sc4808b). in a single controller operation, sync could be grounded or connected to an external synchronization clock within the sync frequency range (see page 3). in the bi-phase operation mode sync pins could be connected to the cosc (timing capacitors) of the other controller. this will force an out of phase operation (see page 15). gnd: device power and analog ground. careful attention should be paid to the layout of the ground planes (see page 22). outa and outb: out of phase gate drive stages. the driver?s peak source and sink current drive capability of 100ma, enables the use of an external mosfet driver or a npn/pnp transistor buffer. the oscillator rc network programs the oscillator frequency, which is twice the outa/outb frequency. to insure that the outputs do not overlap, a dead time can be generated between the two outputs by sizing the oscillator timing ca- pacitor (see page 14). vcc: the supply input for the device. once vcc has ex- ceeded the uvlo limit, the internal reference, oscillator, drivers and logic are powered up. a low esr capacitance, should be used for decoupling right at the ic pin to mini- mize noise problems. pin descriptions
6 ? 2005 semtech corp. www.semtech.com sc4808a/b power management block diagram fb peak current r sq sync ref osc vcc rc r sq soft start outb cs enable uvlo outa luvlo gnd sync bandgap disable luvlo t q q over current luvlo slope comp. r 2r 500mv yyww = datecode (example: 9912) xxxx = semtech lot # (example: e901 xxxx 01-1) top mark yyww xxxx aboa bottom mark marking information xxxx sc4808aimstr, SC4808AIMSTRT top mark yyww xxxx abob bottom mark xxxx sc4808bimstr, sc4808bimstrt
7 ? 2005 semtech corp. www.semtech.com sc4808a/b power management sc4808a typical characteristics (sc4808a) 7 8 9 10 11 12 13 14 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) vcc uvlo (v) vcc uvlo (rising) vcc uvlo (falling) 400 500 600 700 800 900 1000 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) current sense (mv) max current sense signal over current signal 1.42 1.44 1.46 1.48 1.50 1.52 1.54 1.56 1.58 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) fb to cs offset (v) fb to cs offset 5.020 5.030 5.040 5.050 5.060 5.070 5.080 5.090 5.100 5.110 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) reference (v) reference iq (start up) vs. temperature iq (operating) vs. temperature reference vs. temperature fb to cs offset vs. temperature current sense vs. temperature vcc uvlo vs. temperature 3.80 3.90 4.00 4.10 4.20 4.30 4.40 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) iq (ma) operating iq, vcc = 12v operating iq, vcc = 15v 70 75 80 85 90 95 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) iq(ua) start up iq, vcc = 10v
8 ? 2005 semtech corp. www.semtech.com sc4808a/b power management sc4808a typical characteristics (cont.) vcc uvlo hysteresis vs. temperature line uvlo vs. temperature line uvlo hysteresis vs. temperature oscillator frequency vs. temperature synchronization frequency vs. temperature maximum duty cycle vs. temperature 49.0 49.0 49.1 49.1 49.2 49.2 49.3 49.3 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) maximum duty cycle (%) maximum duty cycle 400 500 600 700 800 900 1000 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) synchronization frequency (khz) sync. frequency @ fosc = 500khz 200 400 600 800 1000 1200 1400 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) oscillator frequency (khz) oscillator frequency 1mhz oscillator frequency 500khz 4.985 4.990 4.995 5.000 5.005 5.010 5.015 5.020 5.025 5.030 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) luvlo (v) luvlo (rising) 290 295 300 305 310 315 320 325 330 335 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) luvlo hysteresis (mv) luvlo (hysteresis) 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 5.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) vcc uvlo hysteresis (v) vcc uvlo (hysteresis)
9 ? 2005 semtech corp. www.semtech.com sc4808a/b power management sc4808a typical characteristics (cont.) soft start delay time vs. temperature 80 100 120 140 160 180 200 220 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) soft start delay time (us) soft start delay time
10 ? 2005 semtech corp. www.semtech.com sc4808a/b power management 4.200 4.250 4.300 4.350 4.400 4.450 4.500 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) vcc uvlo (v) vcc uvlo (rising) vcc uvlo (falling) 3.60 3.65 3.70 3.75 3.80 3.85 3.90 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) iq (ma) operating iq, vcc = 5v operating iq, vcc = 5.25v sc4808b typical characteristics (sc4808a) iq (start up) vs. temperature iq (operating) vs. temperature reference vs. temperature fb to cs offset vs. temperature current sense vs. temperature vcc uvlo vs. temperature 400 500 600 700 800 900 1000 1100 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) current sense (mv) max current sense signal over current signal 1.60 1.61 1.62 1.63 1.64 1.65 1.66 1.67 1.68 1.69 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) fb to cs offset (v) fb to cs offset 3.16 3.17 3.18 3.19 3.2 3.21 3.22 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) reference (v) reference, vcc = 5v 70.0 75.0 80.0 85.0 90.0 95.0 100.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) iq(ua) start up iq, vcc = 4v
11 ? 2005 semtech corp. www.semtech.com sc4808a/b power management 100 105 110 115 120 125 130 135 140 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) luvlo hysteresis (mv) luvlo (hysteresis) vcc uvlo hysteresis vs. temperature line uvlo vs. temperature line uvlo hysteresis vs. temperature oscillator frequency vs. temperature synchronization frequency vs. temperature maximum duty cycle vs. temperature sc4808b typical characteristics (cont.) 49.4 49.4 49.4 49.4 49.4 49.5 49.5 49.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) maximum duty cycle (%) maximum duty cycle 650 652 654 656 658 660 662 664 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) synchronization frequency (khz) sync. frequency @ fosc = 500khz 200 400 600 800 1000 1200 1400 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) oscillator frequency (khz) oscillator frequency 1mhz oscillator frequency 500khz 3.120 3.125 3.130 3.135 3.140 3.145 3.150 3.155 3.160 3.165 3.170 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) luvlo (v) luvlo (rising) 84 86 88 90 92 94 96 98 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) vcc uvlo hysteresis (mv) vcc uvlo (hysteresis)
12 ? 2005 semtech corp. www.semtech.com sc4808a/b power management sc4808b typical characteristics (cont.) soft start delay time vs. temperature 80 90 100 110 120 130 140 150 160 170 180 -40 -25 -10 5 20 35 50 65 80 95 110 125 ta (c) soft start delay time (us) soft start delay time
13 ? 2005 semtech corp. www.semtech.com sc4808a/b power management overcurrent comparators. an internal 1 to 3 feedback volt- age divider provides a 3x amplification of the cs signal. this is used for comparison to the external error amplifier signal. if an external resistor is connected from cs to the current sense resistor, the internal current source will pro- vide a programmable slope compensation. the value of the resistor will determine the level of compensation. at higher compensation levels, voltage mode of operation can be achieved. the error amplifier signal at the fb pin will be used in conjunction with the cs signal to achieve regula- tion. two levels of undervoltage lockout are also available. the luvlo (line under voltage lockout) pin via an external re- sistive divider will program the undervoltage lockout level. during the luvlo, the driver outputs are disabled and the softstart is reset. once vcc has exceeded the uvlo (vcc under voltage lock- out) limit, the internal reference, oscillator, drivers and logic are powered up. sync is a positive edge triggered input with a threshold set to 1.6v (sc4808a), and 1.0v (sc4808b). by connecting an external control signal to the sync pin, the internal oscillator frequency will be synchronized to the positive edge of the external control signal. in a single con- troller operation, sync should be grounded or connected to an external synchronization clock within the sync fre- quency range (see page 3). in the bi-phase operation mode a very unique oscillator is utilized to allow two sc4808 to be synchronized together and work out of phase. this feature is setup by simple connection of the sync input to the rc pin of the other part. the fastest oscillator automatically becomes the master, forcing the two pwms to operate out of phase. this feature minimizes the input and output ripples, and reduces stress on the capacitors. e c i v e do l v u c c v . p y te g a t l o v e c n e r e f e r a 8 0 8 4 c s v 0 . 2 1v 5 b 8 0 8 4 c s v 4 . 4v 5 2 1 . 3 theory of operation the sc4808 is a versatile double ended, high speed, low power, pulse width modulator that is optimized for applica- tions requiring minimum space. the device contains all of the control and drive circuity re- quired for isolated or non isolated power supplies where an external error amplifier is used. a fixed oscillator fre- quency (up to 1mhz) can be programmed by an external rc network. the sc4808 is a peak current or voltage mode controller, depending on the amount of slope compensation, programmable with only one external resistor. the cycle by cycle peak current limit prevents core saturation when a transformer is used for isolation while the overcurrent circuitry initiates the softstart cycle. the sc4808 dual output drive stages are arranged in a push-pull configuration. both outputs switch at half the oscillator frequency using a toggle flip flop. the dead time between the two outputs is programmable depending on the values of the timing capacitor and resistors, thus limiting each output stage duty cycle to less than 50%. the sc4808 also provides flexibility with programmable luvlo thresholds, with built-in hysteresis. supply a single supply, vcc is used to provide the bias for the internal reference, oscillator, drivers, and logic circuitry of sc4808. pwm controller sc4808 is a double ended pwm controller that can be used in voltage or current mode applications. two voltage options are available for the sc4808. the sc4808a ver- sion has a typical vcc under voltage of 12.0v and a 5v reference. the sc4808b version provides a 4.4v vcc uvlo, and a 3.125v reference. the oscillator frequency is pro- grammed by a resistor and a capacitor network connected to an external reference provided by the sc4808. the two outputs, outa and outb, are 180 degrees out of phase and run at half of the oscillator frequency. an external error amplifier will provide the error signal to the fb pin of the sc4808. the current sense input and internal slope compensation are both provided via the cs pin. the current sense input from a sense resistor is used for the peak current and application information
14 ? 2005 semtech corp. www.semtech.com sc4808a/b power management vcc under voltage lock out depending on the application and the voltages available, the sc4808a (uvlo = 12.0v), or the sc4808b (uvlo = 4.4v) can be used to provide the vcc undervoltage lock out function to ensure the converters controlled start up. before the vcc uvlo has been reached, the internal refer- ence, oscillator, outa/outb drivers, and logic are disabled. line under voltage lock out the sc4808 also provides a line undervoltage (luvlo = vref) function. the luvlo pin is programmed via an exter- nal resistor divider connected as shown below. the actual start-up voltage can be calculated by using the equation below: () 33 r 33 r 23 r v v ref startup + = r27 15k r24 10k 200p c31 vcc r26 2.2k r28 10 2.2u,16v c26 82p c29 15 ref 0.1u,25v c33 r25 18 r33 10k sync u4 sc4808 4 5 3 2 10 1 6 7 8 9 fb ref cs rc luvlo sync gnd outb outa vcc r23 56.2k vin reference a 5v (sc4808a) or a 3.125v(sc4808b) reference voltage is available that can be used to source a typical current of 5ma to the external circuitry. the vref can be used to pro- vide the oscillator rc network with a regulated bias. application information (cont.) oscillator the oscillator frequency is set by connecting a rc network as shown below. 0 r27 15k 0 200p c31 vcc r28 10 2.2u,16v c26 ref 0.1u,25v c33 r33 10k sync u4 sc4808 4 5 3 2 10 1 6 7 8 9 fb ref cs rc luvlo sync gnd outb outa vcc r23 56.2k vin the oscillator has a ramp voltage of about vref/2. the os- cillator frequency is twice the frequency of the outa and outb gate drive controls. the oscillator capacitor c31 is charged by a current sourced from the vref through r27. once the rc pin reaches about vref/2, the capacitor is discharged internally by the sc4808. it should be noted that larger capacitor values will result in a longer dead time during the down slope of the ramp. the following equation can be used as an approximation of the oscillator frequency and the dead time: 8 . 0 1 _ ? tot osc a osc c r f 9 . 0 1 _ ? tot osc b osc c r f where: circuit sc osc tot c c c c + + = 4808 pf c sc 22 4808 ? 3 10 3 5 . 0 ? ? ? ref osc deadtime v c t the recommended range of timing resistors is between 10 kohm and 200kohm, range of timing capacitors is between 100pf and 1000pf. timing resistors less than 10 kohm should be avoided.
15 ? 2005 semtech corp. www.semtech.com sc4808a/b power management sync/bi-phase operation in noise sensitive applications where synchronization of the oscillator frequency to a reference frequency is required, the sync pin can accept the external clock. by connecting an external control signal to the sync pin, the internal os- cillator frequency will be synchronized to the positive edge of the external control signal. sync is a positive edge trig- gered input with a threshold set to 1.6v (sc4808a), and 1.0v (sc4808b). in a single controller operation, sync should be grounded or connected to an external synchronization clock within the sync frequency range (see page 3). u2 sc4808 4 5 3 2 10 1 6 7 8 9 fb ref cs rc luvlo sync gnd outb outa vcc cosc1 u1 sc4808 4 5 3 2 10 1 6 7 8 9 fb ref cs rc luvlo sync gnd outb outa vcc ref rosc2 ref rosc1 cosc2 in the bi-phase operation mode a very unique oscillator is utilized to allow two sc4808?s to be synchronized together and work out of phase. this feature is set up by a simple connection of the sync input to the rc pin of the other part. the fastest oscillator automatically becomes the master, forcing the two pwms to operate out of phase. this feature minimizes the input and output ripples, and reduces stress on the capacitors. application information (cont.) feed back the error signal from the output of an external error ampli- fier such as sc431 or sc4431 is applied to the inverting input of the pwm comparator at the fb pin either directly or via an opto coupler for the isolated applications. for best stability, keep the fb trace length as short as possible. c39 22n c38 0.1u vref sc4431 1 2 4 5 r35 c36 c35 r34 r36 r38 c37 r32 vout vout c40 22pf r37 2.2k mocd207 3 4 6 5 vref fb the signal at the fb pin is then compared to the 3x ampli- fied signal from the current sense/ slope compensation cs pin. matched out of phase signals are generated to control the outa and outb gate drives of the two phases. a single ramp signal is used to generate the control sig- nals for both phases, hence achieving a tightly matched per phase operation. voltages below 1.5v at the fb pin, will produce a 0% duty cycle at the outa/outb gate drives. this offset is to pro- vide enough head room for the opto coupler used in iso- lated applications. gate drivers outa and outb are out of phase bipolar gate drive output stages, that are supplied from vcc and provide a peak source/sink current of about 100ma. both stages are ca- pable of driving the logic input of external mosfet drivers or a npn/pnp transistor buffer. the output stages switch at half the oscillator frequency. when the voltage on the rc pin is rising, one of the two outputs is high, but during fall time, both outputs are off. this ?dead time? between the two outputs, along with a slower output rise and fall time, insures that the two outputs can not be on at the same time. the dead time is programmable and depends upon the timing capacitor. it should be noted that if high speed/high current drivers such as the sc1301 are used, careful layout guide lines must be followed in order to minimize stray inductance, outa (pwm1) outb (pwm1) outa (pwm2) outb (pwm2)
16 ? 2005 semtech corp. www.semtech.com sc4808a/b power management which might cause negative voltages at the output of the drivers. this negative voltage can be clamped to a reason- able level by placing a small schottky diode directly at the output of the driver as shown below. c34 0.1u vcc vcc u3 sc1301a 1 4 3 2 5 c23 0.1u en u6 sc1301a 1 4 3 2 en vcc r28 10 2.2u,16v c26 f d_a 0.1u,25v c33 r33 10k sync u4 sc4808 4 5 3 2 10 1 6 7 8 9 fb ref cs rc luvlo sync gnd outb outa vcc d_b gate_a 5 gate_b r23 56.2k vin over current two levels of over current protection are provided by the sc4808. the current information is sensed at the cs pin and compared to a peak current limit level of 525mv. if the 525mv limit is exceeded, the outa and outb pulse widths and duty cycle is reduced until the cs pin reaches a second threshold of 950mv. at that point, the outa and outb are disabled, and after a delay of 140s, the inter- nal softstart sequence is started. after the softstart dura- tion (see page 21 for calculation of softstart time), normal operation is achieved, unless the over current condition is still present. application information (cont.)
17 ? 2005 semtech corp. www.semtech.com sc4808a/b power management d<50% instability in current mode operation due to duty cycle >50% i l : inductor current i l : small inductor current perturbation i l i l note: after afew c ycles the perturbation disappears and stable operation returns. d=50% i l i l i l i l note: after afew c ycles the perturbation is still present, although this will cause jitter, but there is no instability. d>50% i l note: after afew c ycles the perturbation becomes larger, and causes instability. i l error tim e error tim e error tim e slope compensation (current or voltage mode of operation) in applications where a current mode control is used for regulation, the peak inductor current information is used to produce the average output current. if a small perturbation due to changes in supply voltage or noise pick up is gener- ated, instability may occur if the duty cycle is >50%. this phenomenon is graphically shown below. the inductor current and disturbed inductor current are shown for three different duty cycles conditions. the top wave form shows the applications where the duty cycle d is less than 50%. as shown, even if an error is introduced, after only a few cycles the error converges to zero. the second wave form shows the case where d = 50%. under this condition, even though the error does not completely disappear, it stays constant and is not getting larger. this will be seen as jitter at the inductor voltage. the bottom wave form shows d>50%. as shown, a very small error results in a much larger error only after a few cycles. this will cause instability in the converter and the average output inductor current. the output load will not be able to be kept in regulation. application information (cont.)
18 ? 2005 semtech corp. www.semtech.com sc4808a/b power management the instability can be corrected by modification of the peak current information slope. one of the methods to alter the peak current information is to add a positive going ramp to the output of the current sensing circuitry. the sc4808 achieves this by using an internal slope com- pensation circuit. the oscillator ramp is internally buffered and an internal 25kohms resistor in conjunction with an external resistor at the cs pin will program the level of slope compensation. rosc 15k r 10k 200p cosc rslope comp 2.2u,16v c 82p cfilter d ref rsense sc4808 4 5 3 2 1 6 7 fb ref cs rc sync gnd n = 100 25k current transformer rslope comp value will determine the mode of operation (voltage or current) the peak current information is sensed and the result is realistically summed to the buffered oscillator ramp, as shown above. the value of the external resistor r slope comp will determine the percentage of the slope compensation. as the value for r slope comp is reduced, the current informa- tion becomes more dominant and the mode of operation becomes more current mode. at the same time the slope of the current information is modified to provide the slope compensation. if the r slope comp is increased, the internal ramp becomes the dominant signal and more voltage mode of operation is application information (cont.) achieved. as it can be calculated from the second formula below, a 100% voltage mode operation can be achieved by choosing r slope comp to be greater than 6.25k ohms. also if a 100% current mode of operation is required, r slope comp is reduced to zero and the contribution from the internal ramp is completely eliminated. () () cs ernal int sense comp _ slope sense comp _ slope ramp v r r r r r v comp _ slope % + + + = or () () ? ? ? ? ? ? ? ? ? comp _ slope % 2 . 0 1 comp _ slope % 2 . 0 r r ernal int external next page illustrates how the buffered oscillator ramp is used to modify the sensed inductor current. it should be noted that in order for the slope compensa- tion to be effective, the current sensed signal slope should be at least 50% less steeper than the oscillator positive ramp slope. the slope will include the magnetizing current of the transformer and the inductor output current in iso- lated applications. in non-isolated applications, the slope will only include the inductor output current.
19 ? 2005 semtech corp. www.semtech.com sc4808a/b power management slope compensation generation from buffered oscillator ramp i l : inductor current : sm all inductor current perturbation i l d>50% i l note: below wave forms are not to scale. i sense : sensed mosfet current buffered oscillator ramp i sense i cs : summation of isense and slope compensation, at the cs pin of the sc4808. i cs application information (cont.)
20 ? 2005 semtech corp. www.semtech.com sc4808a/b power management application information (cont.) below the benefits from the slope compensation become apparent. the top wave form shows the stable operation before the perturbation. the second wave form shows the perturbation and the instability caused from it if no slope compensation is added to the current information. the last wave form shows the slope compensation and the effect of it. the increase in the slope of the current information results in an early termination of the inductor current, hence a reduction in the amount of error. as the cycle is repeated, the perturbation is reduced and finally eliminated. stable current mode operation with slope compensation i l ? : inductor current : small inductor current perturbation i l ? d>50% i l : sensed mosfet current i sense i sense i l i l stable operation ( no perturbation) instable operation ( with perturbation) stable operation (slope compensation added) i l ? i sense i l ? i cs error signal from error amplifier error signal from error amplifier i cs : summation of isense and slope compensation, at the cs pin of the sc4808. error signal from error amplifier note: after a few cycles the perturbation disappears and stable operation returns. note: after a few cycles the perturbation becomes larger, and causes instability.
21 ? 2005 semtech corp. www.semtech.com sc4808a/b power management soft start during start up of the converter, the discharged output ca- pacitor and the load current have large supply current re- quirements. to avoid this a soft start scheme is usually implemented where the duty cycle of the regulator is gradu- ally increased from 0% until the soft start duration is elapsed. sc4808 has an internal soft start circuit that limits the duty cycle for a duration approximated by the formula be- low. also the soft start circuitry is activated if an over cur- rent condition occurs. after an over current condition, outa and outb are disabled and kept low for a duration of about 140s. after the delay, the outa and outb are enabled while the soft start limits the duty cycle. if the over current condition persists, the soft start cycle repeats indefinitely. approximate internal soft start duration can be calculated as below: () ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? 1 r r 2 vref ramp t gnd _ to _ cs slopecomp _ internal softstart softstart if longer soft start durations are required, the simple exter- nal circuit shown below can be implemented. r27 15k 200p c31 vcc r28 10 2.2u,16v c26 ref 0.1u,25v c33 r33 10k sync u4 sc4808 4 5 3 2 10 1 6 7 8 9 fb ref cs rc luvlo sync gnd outb outa vcc r23 56.2k vin 56.2k csoft start ref mocd207 6 5 c40 na r37 1k approximate soft start duration can be calculated as be- low: 37 r c t softstart softstart ? application information (cont.) start up sequence initially during the power up, the sc4808 is in under volt- age lock out condition. as the vcc supply exceeds the uvlo limit of the sc4808, the internal reference, oscillator, and logic circuitry are powered up. the outa and outb drivers are not enabled until the line under voltage lock out limit is reached. at that point, once the fb pin is above 1.5v, soft start circuitry starts the out- put drivers, and gradually increases the duty cycle from 0%. the soft start duration is internally set (see formula in soft start section). as the output voltage starts to increase, the error signal from the error amplifier starts to decrease. if isolation is required, the error amplifier output can drive the led of the opto isolator. the output of the opto is connected in a common emitter configuration with a pull-up resistor to a reference voltage connected to the fb pin of the sc4808. the voltage level at the fb pin provides the duty cycle nec- essary to achieve regulation. if an over current condition occurs, the outputs are dis- abled and after a soft start delay time of about 100s, the softstart sequence mentioned above is repeated.
22 ? 2005 semtech corp. www.semtech.com sc4808a/b power management and secondary ground planes should be used. the same precautions should be followed for the primary gnd plane as mentioned in item 5 mentioned above. for the second- ary gnd plane, the gnd plane method mentioned in item 4 should be followed. 8) all the noise sensitive components such as luvlo re- sistive divider, reference by pass capacitor, vcc bypass ca- pacitor, current sensing circuitry, feedback circuitry, and the oscillator resistor/capacitor network should be con- nected as close as possible to the sc4808. the gnd re- turn should be connected to the quiet sc4808 gnd plane. 9) the connection from the outa and outb of the sc4808 should be minimized to avoid any stray inductance. if the layout can not be optimized due to constraints, a small schottky diode may be connected from the outa/b pins to the ground directly at the ic. this will clamp excessive negative voltages at the ic. if drivers are used, the schottky diodes should be connected directly at the ic from the output of the driver to the driver ground (see page 9). 10) if the sync function is not used, the sync pin should be grounded at the sc4808 gnd to avoid noise pick up. application information (cont.) layout guidelines careful attention to layout requirements are necessary for successful implementation of the sc4808 pwm control- ler. high current switching is present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). the high power parts of the circuit should be laid out first. a ground plane should be used, the number and po- sition of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. iso- lated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, such as the input capacitor and fet ground. 2). in the loop formed by the input capacitor(s) (cin), the fet must be kept as small as possible. this loop contains all the high current, fast transition switching. connections should be as wide and as short as possible to minimize loop inductance. minimizing this loop area will a) reduce emi, b) lower ground injection currents, resulting in electri- cally ?cleaner? grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). the connection between fets and the transformer should be a wide trace or copper region. it should be as short as practical. since this connection has fast voltage transitions, keeping this connection short will minimize emi. 4) the output capacitor(s) (cout) should be located as close to the load as possible. fast transient load currents are supplied by cout only, and connections between cout and the load must be short, wide copper areas to minimize in- ductance and resistance. 5) the sc4808 is best placed over a quiet ground plane area. avoid pulse currents in the cin fet loop flowing in this area. gnd should be returned to the ground plane close to the package and close to the ground side of (one of) the vcc supply capacitor(s). under no circumstances should gnd be returned to a ground inside the cin, q1, q2 loop. avoid making a star connection between the quiet gnd planes that the sc4808 will be connected to and the noisy high current gnd planes connected to the fets. 6) the feed back connection between the error amplifier and the fb pin should be kept as short as possible the gnd connections should be connected to the quiet gnd used for the sc4808. 7) if an opto isolator is used for isolation, quiet primary
23 ? 2005 semtech corp. www.semtech.com sc4808a/b power management gain & phase margin typical sc4808 push pull converter gain/phase plot at vin = 36v, vout = 3.3v, iout = 10a, fosc = 650khz -30 -20 -10 0 10 20 30 40 50 10 100 1000 10000 100000 freq (hz) gain (db) -225 -180 -135 -90 -45 0 45 90 135 180 225 phase (deg) gain phase (deg) gain phase
24 ? 2005 semtech corp. www.semtech.com sc4808a/b power management typical sc4808 push pull converter gain/phase plot at vin = 48v, vout = 3.3v, iout = 10a, fosc = 650khz gain & phase margin (cont.) -30 -20 -10 0 10 20 30 40 50 10 100 1000 10000 100000 freq (hz) gain (db) -225 -180 -135 -90 -45 0 45 90 135 180 225 phase (deg) gain phase (deg) gain phase
25 ? 2005 semtech corp. www.semtech.com sc4808a/b power management gain & phase margin (cont.) typical sc4808 push pull converter gain/phase plot at vin = 72v, vout = 3.3v, iout = 10a, fosc = 650khz -30 -20 -10 0 10 20 30 40 50 10 100 1000 10000 100000 freq (hz) gain (db) -225 -180 -135 -90 -45 0 45 90 135 180 225 phase (deg) gain phase (deg) gain phase
26 ? 2005 semtech corp. www.semtech.com sc4808a/b power management typical step load typical sc4808 push pull converter step load plot at vin = 48v, vout = 3.3v, step = 37% to 75% iout, fosc = 650khz cout = 6x22uf (132uf) ceramic iout 5a/div vout 500mv/div 100us/div
27 ? 2005 semtech corp. www.semtech.com sc4808a/b power management evaluation board schematics sync drive supply 1u,16v c20 .1u,16v c14 m2 sud19n20-90 3 2 1 r4 250 q1 fzt853 e b c c30 1nf r31 16.2 murata grm32dr60j226ka01 d2 mbrb2535ctl 1 3 4 r29 100 con2 3input_half_brick 1 2 4 v in+ on/off vin- d3 1n5819hw a c r19 0 c34 .1uf for output power > 30w, adequate air flow should be provided to avoid over dissipation. sc4808evb__non_sync 1.1 sc4808 push pull 3.3v 50w non synchronous 11 monday, october 07, 2002 title size document number rev date: sheet of semtech corporation d14 cmosh-3 r27 15k vcc = 15v 1u,100v c11 d6 1n5819hw d13 cmosh-3 c24 0.1u r3 20k r12 56.2k 22u,6.3v c6 0.1u,25v c23 g_b n = 100 t2 p8208t 8 7 1 3 g_a m1 sud19n20-90 3 2 1 r23 18.2k 1u,100v c12 grm55dr72e105kw01 r22 37.4k r30 15k d8 ls4448 d11 cmosh-3 j2 0.1u c10 0 j3 c26 0.1u r26 2.2k vcc r21 10k j1 t3 pe-68386 1 3 6 4 r25 11.5k r24 1k c3 2.2n r32 56.2k 0.1u c2 r8 0 vcc 2.2u,16v c19 d15 cmosh-3 r18 10 d12 cmosh-3 sync drive supply r5 10 d1 mbrb2535ctl 1 3 4 c35 2.2uf 16v vref u5 sc4431 1 2 4 5 d4 zm4743a 22u,6.3v c7 d16 1n5819hw a c ref ref u3 sc1301a 1 4 3 2 5 r17 15k r6 tbd u1 sc4808 4 5 3 2 10 1 6 7 8 9 fb ref cs rc luvlo sync gnd outb outa vcc d7 cmosh-3 d9 cmosh-3 u2 sc1301a 1 4 3 2 5 22u,6.3v c9 r7 0 c32 0.1u r13 10k 82p c22 u7 cbrhd-02 1 2 3 4 c1 2.2n r1 0 r9 2.2 jp1 sync g_b c28 na vref u4 sc4431 1 2 4 5 l2 lqh43mn102k011 1 2 22u,6.3v c4 r15 0 r20 2.2k sync drive supply r11 tbd r16 1k r10 2.2 r28 25.5k q2 fmmt718 22u,6.3v c8 vcc d10 cmosh-3 10u,16v c15 grm32dr61c106ka01 82p c21 c25 10nf 22nf c18 r2 10 u6 mocd207 1 2 8 7 3 4 6 5 10u,16v c16 grm32dr61c106ka01 c17 0.1u g_a vcc vcc c29 100pf 22u,6.3v c5 d5 1n5819hw con1 5output_half_brick 5 6 7 8 9 vout- sense- trim sense+ vout+ c27 22n c31 470pf c33 22n 6t 1t 4t t1 pa0500 2 5 3 4 10 9 8 1 6 r14 15 1u,100v c13 grm55dr72e105kw01 note: l1 0.9uh 1 2 0 ref 6t 1t pg0006.102t
28 ? 2005 semtech corp. www.semtech.com sc4808a/b power management evaluation board bill of materials sc4808 push pull 3.3v 50w non synchronous sc4808evb__non_sync revision: 1.1 bill of materials october 7,2002 13:35:18 1 1 con1 5output_half_brick con\5output_half_brick 2 1 con2 3input_half_brick con\3input_half_brick 3 2 c3,c1 2.2n sm/c_1206 4 6 c2,c10,c17,c24,c26,c32 0.1u sm/c_0805 5 6 c4,c5,c6,c7,c8,c9 22u,6.3v grm32dr60j226ka01 sm/c_1210_grm 6 3 c11,c12,c13 1u,100v grm55dr72e105kw01 sm/c_2220 7 1 c14 .1u,16v sm/c_0805 8 2 c15,c16 10u,16v grm32dr61c106ka01 sm/c_1210_grm 9 1 c18 22nf sm/c_1206 10 1 c19 2.2u,16v sm/c_1206 11 1 c20 1u,16v grm32rr71h105ka011 sm/c_1210_grm 12 2 c22,c21 82p sm/c_0805 13 1 c23 0.1u,25v sm/c_1206 14 1 c25 10nf sm/c_0805 15 2 c27,c33 22n sm/c_0805 16 1 c28 na sm/c_0805 17 1 c29 100pf sm/c_0805 18 1 c30 1nf sm/c_0805 19 1 c31 470pf sm/c_0805 20 1 c34 .1uf sm/c_0805 21 1 c35 2.2uf 16v sm/c_0805 22 2 d2,d1 mbrb2535ctl diode_d2pak 23 4 d3,d5,d6,d16 1n5819hw sod123 24 1 d4 zm4743a smb/do214 25 8 d7,d9,d10,d11,d12,d13, cmosh-3 cmosh-3 (central semiconductor) sod523 d14,d15 26 1 d8 ls4448 sm/do213ac 27 1 jp1 short via\2p 28 1 j1 ref ed5052 29 1 j2 vcc ed5052 30 1 j3 sync ed5052 31 1 l1 0.9uh pg0006 32 1 l2 lqh43mn102k011 lqh43mn102k01l sdip0302 33 2 m1,m2 sud19n20-90 sud19n20-90 dpakfet 34 1 q1 fzt853 sm/sot223_bcec 35 1 q2 fmmt718 36 4 r1,r7,r15,r19 0 sm/r_0805 37 2 r5,r2 10 sm/r_1206 38 1 r3 20k sm/r_1206 39 1 r4 250 sm/r_1210_mcr 40 2 r6,r11 tbd sm/r_0805 41 1 r8 0 sm/r_1206 42 2 r9,r10 2.2 sm/r_0805 43 1 r12 56.2k sm/r_1206 44 1 r13 10k sm/r_0805 45 1 r14 15 sm/r_0805 46 2 r16,r24 1k sm/r_0805 47 3 r17,r27,r30 15k sm/r_0805 48 1 r18 10 sm/r_0805 49 2 r26,r20 2.2k sm/r_0805 50 1 r21 10k sm/r_1206 51 1 r22 37.4k sm/r_0805 52 1 r23 18.2k sm/r_0805 53 1 r25 11.5k sm/r_0805 54 1 r28 25.5k sm/r_0805 55 1 r29 100 sm/r_0805 56 1 r31 16.2 sm/r_1206 57 1 r32 56.2k sm/r_0805 58 1 t1 pa0500 pa0500 59 1 t2 p8208t p8208t 60 1 t3 pe-68386 pe-68386 61 1 u1 sc4808 msop10 62 2 u2,u3 sc1301a sot23_5pin 63 2 u4,u5 sc4431 sot23_5pin 64 1 u6 mocd207 so-8 65 1 u7 cbrhd-02 cbrhd-02 manufacturer # foot print item quantity reference part
29 ? 2005 semtech corp. www.semtech.com sc4808a/b power management evaluation board gerber plots board layout assembly top board layout assembly bottom board layout top board layout bottom
30 ? 2005 semtech corp. www.semtech.com sc4808a/b power management evaluation board gerber plots board layout inner1 board layout inner2
31 ? 2005 semtech corp. www.semtech.com sc4808a/b power management outline drawing - msop-10 semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 contact information bbb c a-b d dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view a b c d h plane 0 .010 .004 - .016 .003 .024 (.037) - .000 .030 - - - - 0.25 0.10 8 0 - 8 0.60 (.95) .032 .009 0.40 0.08 .043 .006 .037 0.75 0.00 - 0.80 0.23 - 0.95 1.10 0.15 - - - e .193 bsc .020 bsc detail aaa c seating indicator ccc c 2x n/2 tips pin 1 2x e/2 10 see detail a1 a a2 bxn d 0.25 a plane gage .003 e1 12 n .114 .114 .118 .118 .007 - 10 01 c (l1) l a 0.08 3.00 3.00 4.90 bsc 0.50 bsc .122 .122 2.90 2.90 .011 0.17 3.10 3.10 0.27 - reference jedec std mo-187, variation ba. 4. dim ccc a1 e bbb aaa 01 l1 n l d e1 e a2 b c a millimeters nom inches dimensions min nom max min max e this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. p (c) x z g y .063 .224 .011 .020 .098 (.161) 5.70 1.60 0.30 0.50 2.50 (4.10) millimeters dimensions dim inches y z g p x c land pattern - msop-10

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